The present invention relates generally to integrated circuit testing, and more specifically, to design-based weighting for logic built-in self-test (LBIST).
LBIST is used to test integrated circuit logic of high-end servers and computers. LBIST is used at all levels of test including: integrated circuit, multi-chip module (MCM), and system levels. Conceptually, the LBIST approach is based on the realization that much of a circuit tester's electronics is semi-conductor based, just like the devices under test, and that many of the challenges and limitations of testing lie in the interface to the Device Under Test (DUT). The LBIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the DUT and eliminate complex interfacing. One of the major advantages LBIST has over other means of testing logic is that operation of the test is self-contained. All of the circuitry required to execute the test at-speed is contained within the integrated circuit. Very limited external controls are needed, so LBIST can be run at all levels of packaging (e.g., wafer, module and system) without requiring expensive external test equipment.
LBIST utilizes what is commonly referred to as Self-Test Using Multiple Signal Registers and Pseudo-Random Pattern Generators (STUMPS) architecture. The major components of LBIST include: a pseudo-random pattern generator (PRPG) used to generate the test patterns; a multiple input signature register (MISR) to compress the test results; and the self-test control macro (STCM) that is used to apply clocks and controls to the PRPG, MISR and system logic to perform the test. The PRPG applies test data to the system logic via multiple parallel scan chains, which are connected between the PRPG and MISR.
One of the limitations of LBIST is the maximum achievable test coverage. Because the PRPG is implemented using a linear feedback shift register (LFSR) that generates random patterns (i.e., 50% chance of being a 0 or a 1), certain random resistant structures are difficult, if not impossible, to test. Examples include very wide AND gates or OR gates where the probability of all inputs being a 1 in the case of an AND gate or all inputs being a 0 in the case of an OR gate is very small. Typically, LBIST test coverage peaks at around 96%. The remaining faults must be tested by some other means of logic test, either weighted random pattern test (WRPT), deterministic test, or a combination of both.
Weighting is a technique where patterns can be biased towards a 0 or 1 state by ANDing or ORing multiple bits of an LFSR together. Instead of a 50% chance of a 0 or a 1, the odds of a 0 or 1 are weighted to increase the probability of one or the other occurring. For example, if 3 random bits are ORed together, the resultant output has a 7/8 chance of being a 1. Conversely, if 4 random bits are ANDed together, the output has a 1/16 chance of being a 1. This weighting technique can be used to test random resistant structures such as large AND or OR structures.
In contemporary designs, many LBIST variations are used in manufacturing tests employing different weights. As one example, U.S. Pat. No. 6,671,838, “Method and Apparatus for Programmable LBIST Channel Weighting” filed Sep. 27, 2000, which is incorporated herein by reference, teaches a built-in self-test (BIST) method and apparatus for testing logic circuits on an integrated circuit, where a random resistant fault analysis (RRFA) program is used to determine weighting requirements on a per channel basis. In U.S. Pat. No. 6,671,838, weighting requirements from the RRFA program are applied to random test pattern data resulting in weighted test pattern data that is programmably applied to a scan chain.